Microprocessor architectures are successful when they enable maximum scaling of both software productivity and transistor device physics. CISC enabled assembly programmers to fit efficient code into a limited memory foot print, whereas RISC enable programmers to write millions of lines of code that could be scheduled in small simple steps on high frequency (MHz) pipelined Out-of-Order CPUs. However, CPU scaling was declared dead when the power wall forced CISC- and RISC-based designs into multi-core implementations that require unrealistically complex multi-threading of sequential applications. VISC Architecture revives CPU power-performance scaling by utilizing virtual cores and virtual hardware threading automatically under the hood with no impact to the software programmer.
The VISC architecture, based on the concept of virtual cores and virtual hardware threads, enables dynamic allocation and sharing of resources across cores. Microprocessors based on CISC and RISC architectures make use of physical cores and software threads, an approach that has been technologically and economically hamstrung by transistor utilization, frequency and power-scaling limitations. The VISC architecture achieves 3-4 times more instructions per cycle (IPC), resulting in 2-4 times higher performance per watt on single- and multi-threaded applications. Moreover, VISC uses a light-weight virtual software layer that makes VISC architecture applicable to existing as well as new software ecosystems.
Soft Machines VISC virtual cores are not bound by physical limitations of traditional CPU cores, which brings not only significant improvements in performance, but also brings meaningful improvements in power efficiency.
The VISC virtual cores, which automatically generate virtual hardware threads under the hood without affecting ecosystem software or requiring software rewrites, is significantly more efficient than software multi-threading.
VISC uses a light-weight virtual software layer that makes VISC architecture applicable to existing ISAs as well as new software ecosystems.